1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various methods of forming high mobility fin channels on three dimensional (3D) semiconductor devices, such as, for example, FinFET semiconductor devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If there is no voltage applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents which are relatively small). However, when an appropriate voltage is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, there are so-called 3D devices, such as an illustrative FinFET device, which is a 3-dimensional structure. More specifically, in a FinFET, a generally vertically positioned fin-shaped active area is formed and a gate electrode encloses both sides and an upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a 3-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to reduce at least some short channel effects.
The use of materials other than silicon for FinFET devices has been attempted. For example, it has been contemplated to manufacture at least part of a FinFET device from so-called “III-V” materials. However, there have been several problems associated with such devices, and particularly the manufacturing of such devices. One problem associated with manufacturing devices from such III-V material is that such materials are very difficult to etch to the very small and controllable feature sizes required in current-day devices and products. Additionally, problems have been encountered when attempting to epitaxially grow a III-V material, such as gallium arsenide, on a crystalline silicon material. The crystals in a typical III-V material are much larger than the crystals in a crystalline semiconductor material. This mismatch in crystal size causes the formation of a relatively large number of defects, such as point defects, in epitaxially grown III-V material. These defects tend to be so-called mid-point defects which, among other things, tends to make the III-V material very difficult to etch. In some cases, efforts have been made to alleviate this problem by forming a buffer layer on the silicon surface and thereafter forming the III-V material above the buffer layer. The buffer layer is typically made of a material, such as indium nitride, that has a crystal size that is intermediate the silicon and the III-V material, such as gallium arsenide. However, the use and formation of such buffer layers makes the manufacturing of modern integrated circuits with very small feature sizes even more difficult and problematic, and the use of such buffer layers in manufacturing has not achieved widespread success.
The present disclosure is directed to various methods of forming high mobility semiconductor fins on three dimensional (3D) semiconductor devices, such as, for example, FinFET semiconductor devices, that may solve or at least reduce one or more of the problems identified above.